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Integrated Circuit Systems, Inc.
ICS950902
Programmable Timing Control HubTM for P4TM
Recommended Application: VIA P4X/P4M/KT/KN266/333 style chipsets. Output Features: * 1 - Pair of differential CPU clocks @ 3.3V (CK408)/ 1 - Pair of differential open drain CPU clocks (K7) * 1 - Pair of differential push pull CPU_CS clocks @ 2.5V * 3 - AGP @ 3.3V * 7 - PCI @ 3.3V (1 - Free running) * 1 - 48MHz @ 3.3V fixed * 1 - 24_48MHz @ 3.3V (Default 48MHz I2C select only) * 2 - REF @ 3.3V, 14.318MHz * 12 - SDRAM (6 pair - DDR) selectable Key Specifications: * CPU_CS - CPUT/C: <250ps * CPU_CS - AGP: <250ps * CPU - DDR/SD: <250ps * PCI - PCI: <500ps * CPU - PCI: Min = 1.0ns, Typ = 2.0ns, Max = 4.0ns Features/Benefits: * Programmable output frequency. * Programmable output divider ratios. * Programmable output rise/fall time. * Programmable output skew. * Programmable spread percentage for EMI control. * DDR output buffer supports up to 200MHz. * Watchdog timer technology to reset system if system malfunctions. * Programmable watch dog safe frequency. * Support I2C Index read/write and block read/write operations. * Uses external 14.318MHz crystal.
Frequency Table
FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPUCLK MHz 160.00 164.00 166.60 170.00 175.00 180.00 185.00 190.00 66.80 100.90 133.60 200.40 66.60 100.00 200.00 133.30 AGP MHz 80.00 82.00 66.60 68.00 70.00 72.00 74.00 76.00 66.80 67.27 66.80 66.80 66.60 66.60 66.60 66.60 PCICLK MHz 40.00 41.00 33.30 34.00 35.00 36.00 37.00 38.00 33.40 33.63 33.40 33.40 32.30 33.30 33.30 33.30
Pin Configuration
*FS0/REF0 1 GND 2 X1 3 X2 4 VDDAGP 5 *MODE/AGPCLK0 6 *SEL_408/K7/AGPCLK1 7 *(PCI_STOP#)AGPCLK2 8 GNDAGP 9 **FS1/PCICLK_F 10 **SEL_SDR/DDR#/PCICLK1 11 GNDPCI 13 PCICLK3 14 PCICLK4 15 VDDPCI 16 PCICLK5 17 *(CLK_STOP#)PCICLK6 18 GND48 19 *FS3/48MHz 20 *FS2/24_48MHz 21 AVDD48 22 VDD 23 GND 24 IREF 25 *(PD#)RESET# 26 SCLK 27 *MULTSEL/PCICLK2 12 56 Vtt_PWRGD#**/REF1 55 VDDREF 54 GND 53 CPUCLKT/CPUCLKODT 52 CPUCLKC/CPUCLKODC 51 VDDCPU3.3 50 VDDCPU2.5 49 CPUC_CS 48 CPUT_CS 47 GND 46 FBOUT 45 BUF_IN 44 DDRT0/SDRAM0 43 DDRC0/SDRAM1 42 DDRT1/SDRAM2 41 DDRC1/SDRAM3 40 VDD3.3_2.5 39 GND 38 DDRT2/SDRAM4 37 DDRC2/SDRAM5 36 DDRT3/SDRAM6 35 DDRC3/SDRAM7 34 VDD3.3_2.5 33 GND 32 DDRT4/SDRAM8 31 DDRC4/SDRAM9 30 DDRT5/SDRAM10 29 DDRC5/SDRAM11
MULTISEL0
Board Target Trace/Term Z 50 ohms 50 ohms
Reference R, Iref = VDD/(3*Rr) Rr = 221 1%, Iref = 5.00mA Rr = 475 1%, Iref = 2.32mA
Output Current Ioh = 4* I REF Ioh = 6* I REF
Voh @ Z
SDATA 28
0 1
1.0V @ 50 0.7V @ 50
56-Pin 300-mil SSOP & 240-mil TSSOP
* Internal 120K pull-up resistor to VDD. ** Internal 120K pull-down resistor to GND.
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ICS950902
Integrated Circuit Systems, Inc.
ICS950902
General Description
The ICS950902 is a single chip clock solution for desktop designs using the VIA P4X/P4M/KT/KN266/333 style chipsets with PC133 or DDR memory. The ICS950902 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Block Diagram
FBOUT DDRC (5:0)/SDRAM (11,9,7,5,3,1) DDRC (5:0)/SDRAM (10,8,6,4,2,0)
Power Groups
Pin Number VDD 55 5 16 22 23 34, 40 50 51
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GND 2 9 13 19 24 33, 39 47 54
Description Xtal, Ref AGP [0:2], CPU digital, CPU PLL PCI [0:5], PCI_F outputs 48MHz, Fix Digital, Fix Analog Master clock, CPU Analog DDR/SDR outputs 2.5V CPUT/C_CS output 3.3V CPUT/C & CPUOD_T/C
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ICS950902
Pin Description
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PIN NAME *FS0/REF0 GND X1 X2 VDDAGP *MODE/AGPCLK0 *SEL_408/K7/AGPCLK1 *(PCI_STOP#)AGPCLK2 GNDAGP **FS1/PCICLK_F **SEL_SDR/DDR#/PCICLK1 *MULTSEL/PCICLK2 GNDPCI PCICLK3 PCICLK4 VDDPCI PCICLK5 *(CLK_STOP#)PCICLK6 GND48 *FS3/48MHz *FS2/24_48MHz AVDD48 VDD GND IREF PIN TYPE I/O PWR IN OUT PWR I/O I/O I/O PWR I/O I/O I/O PWR OUT OUT PWR OUT I/O PWR I/O I/O PWR PWR PWR OUT DESCRIPTION Frequency select latch input pin / 14.318 MHz reference clock. Ground pin. Crystal input,nominally 14.318MHz. Crystal output, Nominally 14.318MHz Power supply for AGP clocks, nominal 3.3V Function select latch input pin, 1=Desktop Mode, 0=Mobile Mode / AGP clock output. CPU output type select latch input pin 0= K7, 1= CK408 / AGP clock output. Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low. This input is activated by the MODE selection pin / AGP clock output. Ground pin for the AGP outputs Frequency select latch input pin / 3.3V PCI free running clock output. Memory type select latch input pin 0= DDR, 1= PC133 SDRAM / 3.3V PCI clock output. 3.3V LVTTL input for selection the current multiplier for CPU outputs / 3.3V PCI clock output. Ground pin for the PCI outputs PCI clock output. PCI clock output. Power supply for PCI clocks, nominal 3.3V PCI clock output. Stops all CPU, DDR/SDRAM and FB_OUT clocks at logic 0 level, when input low. This input is activated by the MODE selection pin / PCI clock output. Ground pin for the 48MHz outputs Frequency select latch input pin / Fixed 48MHz clock output. 3.3V Frequency select latch input pin / Fixed 24 or 48MHz clock output. 3.3V. Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V Power supply, nominal 3.3V Ground pin. This pin establishes the reference current for the CPUCLK pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. Asynchronous active low input pin used to power down the device into a low power state. This input is activated by the MODE selection pin / Real time system reset signal for frequency gear ratio change or watchdog timer timeout. This signal is active low. Clock pin of I2C circuitry 5V tolerant Data pin for I2C circuitry 5V tolerant
26 27 28
*(PD#)RESET# SCLK SDATA
I/O IN I/O
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This output has 2X drive strength
Pin description continued on next page.
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ICS950902
Pin Description Continued
PIN # 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 PIN NAME DDRC5/SDRAM11 DDRT5/SDRAM10 DDRC4/SDRAM9 DDRT4/SDRAM8 GND VDD3.3_2.5 DDRC3/SDRAM7 DDRT3/SDRAM6 DDRC2/SDRAM5 DDRT2/SDRAM4 GND VDD3.3_2.5 DDRC1/SDRAM3 DDRT1/SDRAM2 DDRC0/SDRAM1 DDRT0/SDRAM0 BUF_IN FBOUT GND CPUT_CS CPUC_CS VDDCPU2.5 VDDCPU3.3 CPUCLKC/CPUCLKODC PIN TYPE OUT OUT OUT OUT PWR PWR OUT OUT OUT OUT PWR PWR OUT OUT OUT OUT IN OUT PWR OUT OUT PWR PWR OUT DESCRIPTION "Complementary" Clock of differential memory output / 3.3V SDRAM clock output "True" Clock of differential memory output / 3.3V SDRAM clock output "Complementary" Clock of differential memory output / 3.3V SDRAM clock output "True" Clock of differential memory output / 3.3V SDRAM clock output Ground pin. 2.5V or 3.3V nominal power supply voltage. "Complementary" Clock of differential memory output / 3.3V SDRAM clock output "True" Clock of differential memory output / 3.3V SDRAM clock output "Complementary" Clock of differential memory output / 3.3V SDRAM clock output "True" Clock of differential memory output / 3.3V SDRAM clock output Ground pin. 2.5V or 3.3V nominal power supply voltage. "Complementary" Clock of differential memory output / 3.3V SDRAM clock output "True" Clock of differential memory output / 3.3V SDRAM clock output "Complementary" Clock of differential memory output / 3.3V SDRAM clock output "True" Clock of differential memory output / 3.3V SDRAM clock output Input Buffers for memory outputs. Memory feed back output. Ground pin. "True" clocks of differential pair 2.5V push-pull CPU outputs. Complementary" clocks of differential pair 2.5V push-pull CPU outputs. Power pin for the CPUCLKs. 2.5V Power pin for the CPUCLKs. 3.3V "Complementary" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias / "Complementary" clocks of differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up / 2.5V CPU clock output. "True" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias / "True" clocks of differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up / 2.5V CPU clock output. Ground pin. Ref, XTAL power supply, nominal 3.3V This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. This is an active low input. / 14.318 MHz reference clock.
53 54 55 56
CPUCLKT/CPUCLKODT GND VDDREF Vtt_PWRGD#**/REF1
OUT PWR PWR IN
Mode Pin - Power Management Input Control
MODE, Pin 6 (Latched Input) 0 1 Pin 26 PD# (Input) RESET# (Output) Pin 18 CLK_STOP# (Input) PCICLK6 (Output) Pin 8 PCI_STOP# (Input) AGP2 (Output)
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ICS950902
General I2C serial interface information How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P Not acknowledge stoP bit
*See notes on the following page.
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ICS950902
Byte 0: Functionality and frequency select register (Default=0)
Bit Description Bit2 Bit7 Bit6 Bit5 Bit4 CPUCLK AGPCLK PCICLK MHz MHz MHz FS4 FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0101010 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Frequency is selected by Frequency is selected by Normal Spread spectrum enable Running Tristate all outputs Spread % PWD
Bit (2,7:4)
Bit 3 Bit 1 Bit 0
102.00 68.00 34.00 +/- 0.30% Center Spread 105.00 70.00 35.00 +/- 0.30% Center Spread 108.00 72.00 36.00 +/- 0.30% Center Spread 111.00 74.00 27.00 +/- 0.30% Center Spread 114.00 76.00 38.00 +/- 0.30% Center Spread 117.00 78.00 39.00 +/- 0.30% Center Spread 120.00 80.00 40.00 +/- 0.30% Center Spread 123.00 82.00 41.00 +/- 0.30% Center Spread 126.00 72.00 36.00 +/- 0.30% Center Spread 130.00 74.30 37.10 +/- 0.30% Center Spread 133.90 66.95 33.48 +/- 0.30% Center Spread 140.00 70.00 35.00 +/- 0.30% Center Spread 144.00 72.00 36.00 +/- 0.30% Center Spread 148.00 74.00 37.00 +/- 0.30% Center Spread 152.00 76.00 38.00 +/- 0.30% Center Spread 156.00 78.00 39.00 +/- 0.30% Center Spread 160.00 80.00 40.00 +/- 0.30% Center Spread 164.00 82.00 41.00 +/- 0.30% Center Spread 166.60 66.60 33.30 +/- 0.30% Center Spread 170.00 68.00 34.00 +/- 0.30% Center Spread 175.00 70.00 35.00 +/- 0.50% Center Spread 180.00 72.00 36.00 +/- 0.50% Center Spread 185.00 74.00 37.00 +/- 0.50% Center Spread 190.00 76.00 38.00 +/- 0.30% Center Spread 66.80 66.80 33.40 +/- 0.30% Center Spread 100.90 67.27 33.63 +/- 0.30% Center Spread 133.60 66.80 33.40 +/- 0.30% Center Spread 200.40 66.80 33.40 +/- 0.30% Center Spread 66.60 66.60 32.30 0 to - 0.6% Down Spread 100.00 66.60 33.30 0 to - 0.6% Down Spread 200.00 66.60 33.30 0 to - 0.6% Down Spread 133.30 66.60 33.30 0 to - 0.6% Down Spread hardware select, latched inputs Bit 2,7:4
Note 1
0 1 0
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
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ICS950902
Byte 1: CPU Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Pin# 29 10 30 31 32 53, 52 48, 49
PWD 1 1 1 1 1 1 1 1
Description SDRAM11/DDRC5 (Active/Inactive) PCICLK_F (Active/Inactive) SDRAM10/DDRT5 (Active/Inactive) SDRAM9/DDRC4 (Active/Inactive) (Reserved) SDRAM8/DDRT4 (Active/Inactive) CPUCLKT/C_CS (Active/Inactive) CPUCLKT/C_CS (Active/Inactive)
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Pin# 46 18 17 15 14 12 11 53, 52 PWD 1 1 1 1 1 1 1 1 Description FB_OUT Free running control; 1 = free running; 0 = not free running PCICLK6 (Active/Inactive) PCICLK5 (Active/Inactive) PCICLK4 (Active/Inactive) PCICLK3 (Active/Inactive) PCICLK2 (Active/Inactive) PCICLK1 (Active/Inactive) CPUCLKT/C Free running control; 1 = free running; 0 = not free running
Byte 3: Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Pin# 46 56 48, 49 8 7 6 PWD 1 1 1 1 1 1 1 1 Description FB_OUT (Active/Inactive) SEL 24_48, 0=24Mhz 1=48MHz SD/DDR free running control; 1 = free running; 0 not free running REF1 (Active/Inactive) CPUC/T_CS free running control; 1 = free running; 0 not free running AGPCLK 2 (Active/Inactive) AGPCLK 1 (Active/Inactive) AGPCLK 0 (Active/Inactive)
Byte 4: Frequency Select Active/Inactive Register (1 = enable, 0 = disable)
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
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Pin# 20 21 1
PWD X X X X 1 1 1
Description Latched FS3 Latched FS2 Latched FS1 Latched FS0 48MHz (Active/Inactive) 24_48MHz (Active/Inactive) (Reserved) REF0 (Active/Inactive)
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ICS950902
Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable)
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Pin# 35 36 37 38 41 42 43 44
PWD 1 1 1 1 1 1 1 1
Description SDRAM7/DDRC3 (Active/Inactive) SDRAM6/DDRT3 (Active/Inactive) SDRAM5/DDRC2 (Active/Inactive) SDRAM4/DDRT2 (Active/Inactive) SDRAM3/DDRC1 (Active/Inactive) SDRAM2/DDRT1 (Active/Inactive) SDRAM1/DDRC0 (Active/Inactive) SDRAM0/DDRT0 (Active/Inactive)
Byte 6: Vendor ID Register (1 = enable, 0 = disable)
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name Revision ID Bit3 Revision ID Bit2 Revision ID Bit1 Revision ID Bit0 Vendor ID Bit3 Vendor ID Bit2 Vendor ID Bit1 Vendor ID Bit0 PWD X X X X 0 0 0 1 Description Revision ID values will be based on individual device's revision (Reserved) (Reserved) (Reserved) (Reserved)
Byte 7: Revision ID and Device ID Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Device ID7 Device ID6 Device ID5 Device ID4 Device ID3 Device ID2 Device ID1 Device ID0
PWD Description 0 0 0 Device ID values will be based on individual device 1 "01h" in this case. 0 1 1 1
Byte 8: Byte Count Read Back Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
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Name Byte7 Byte6 Byte5 Byte4 Byte3 Byte2 Byte1 Byte0
PWD Description 0 0 0 Note: Writing to this register will configure byte count and how 0 many bytes will be read back, default is 0FH = 15 bytes. 1 1 1 1
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Integrated Circuit Systems, Inc.
ICS950902
Byte 9: Watchdog Timer Count Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0
PWD Description 0 0 0 The decimal representation of these 8 bits correspond to X * 0 290ms the watchdog timer will wait before it goes to alarm mode and reset the frequency to the safe setting. Default at power up is 1 16 * 290ms = 4.6 seconds. 0 0 0
Byte 10: Programming Enable bit 8 Watchdog Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Program Enable WD Enable WD Alarm S F4 S F3 S F2 S F1 S F0
PWD 0 0 0 0 0 0 0 1
Description Programming Enable bit 0 = no programming. Frequencies are selected by HW latches or Byte0 1 = enable all I2C programing. Software Watchdog Enable bit. This bit will over write WDEN latched value. 0 = disable, 1 = Enable. Watchdog Alarm Status 0 = normal 1= alarm status Watchdog safe frequency bits. Writing to these bits will configure the safe frequency corrsponding to Byte 0 Bit 2, 7:4 table
Byte 11: VCO Frequency M Divider (Reference divider) Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Ndiv 8 Mdiv 6 Mdiv 5 Mdiv 4 Mdiv 3 Mdiv 2 Mdiv 1 Mdiv 0
PWD X X X X X X X X
Description N divider bit 8
The decimal respresentation of Mdiv (6:0) corresposd to the reference divider value. Default at power up is equal to the latched inputs selection.
Byte 12: VCO Frequency N Divider (VCO divider) Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
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Name Ndiv 7 Ndiv 6 Ndiv 5 Ndiv 4 Ndiv 3 Ndiv 2 Ndiv 1 Ndiv 0
PWD Description X X X The decimal representation of Ndiv (8:0) correspond to the X VCO divider value. Default at power up is equal to the latched inputs selecton. Notice Ndiv 8 is located in Byte 11. X X X X
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ICS950902
Byte 13: Spread Spectrum Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name SS 7 SS 6 SS 5 SS 4 SS 3 SS 2 SS 1 SS 0
PWD Description X X The Spread Spectrum (12:0) bit will program the spread X precentage. Spread precent needs to be calculated based on the X VCO frequency, spreading profile, spreading amount and spread X frequency. It is recommended to use ICS software for spread X programming. Default power on is latched FS divider. X X
Byte 14: Spread Spectrum Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Reserved Reserved Reserved SS 12 SS 11 SS 10 SS 9 SS 8
PWD X X X X X X X X
Description Reserved Reserved Reserved Spread Spectrum Bit 12 Spread Spectrum Bit 11 Spread Spectrum Bit 10 Spread Spectrum Bit 9 Spread Spectrum Bit 8
Byte 15: Output Divider Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name CPU Div 3 CPU Div 2 CPU Div 1 CPU Div 0 CPU Div 3 CPU Div 2 CPU Div 1 CPU Div 0
PWD 0 1 0 1 0 1 0 1
Description CPUCLKC/T clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider. CPUCLKT/C_CS clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider.
Byte 16: Output Divider Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name AGP Div 3 AGP Div 2 AGP Div 1 AGP Div 0 Reser ved Reser ved Reser ved Reser ved
PWD 0 1 0 1 -
Description AGP clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider.
Reser ved
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ICS950902
Byte 17: Output Divider Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name AGP_INV Reserved CPU_INV CPU_INV
PWD 0 0 0 0
Description AGP Phase Inversion bit Reserved CPU T/C Phase Inversion bit CPUT/C_CS Phase Inversion bit
PCI Div 3 PCI Div 2 PCI Div 1 PCI Div 0
1 0 0 1
PCI clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 2. Default at power up is latched FS divider.
Table 1
Table 2
Div (3:2) Div (1:0) 00 01 10 11
00 /2 /3 /5 /7
01 /4 /6 /10 /14
10 /8 /12 /20 /28
11 /16 /24 /40 /56
Div (3:2) Div (1:0) 00 01 10 11
00 /4 /3 /5 /9
01 /8 /6 /10 /18
10 /16 /12 /20 /36
11 /32 /24 /40 /72
Byte 18: Group Skew Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name CPUCLKT/C_CS Group Skew Control CPUCLKT/C Group Skew Control AGPCLK Group Skew Control Reserved Reserved
PWD 1 0 1 0 1 0 X X
Description These 2 bits delay the CPUCLKT/C_CS with respect to CPUCLKT/C_CS 00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps These 2 bits delay the CPUCLKT/C clock with respect to CPUCLKT/C_CS 00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps These 2 bits delay the AGPCLK clocks with respect to CPUCLK 00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps Reserved Reserved
Byte 19: Group Skew Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
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Name Reserved
PCICLK(5:0) Group Skew Control
PWD Description 1 0 Reserved 0 0 1 These 4 bits can change the CPU to PCI (5:0) skew from 1.4ns 0 2.9ns. Default at power up is - 2.5ns. Each binary increment or decrement of Bits (3:0) will increase or decrease the delay of the 0 PCI clocks by 100ps. 0
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ICS950902
Byte 20: Group Skew Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name PCICLK_F Group Skew Control PWD Description 1 These 4 bits can change the CPU to PCIF skew from 1.4ns 0 2.9ns. Default at power up is - 2.5ns. Each binary increment or decrement of Bit (3:0) will increase or decrease the delay of the 0 PCI clocks by 100ps. 0 1 0 Reserved 0 0
Reserved
Byte 21: Slew Rate Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name CPUCLKT/C_CS Slew Rate Control CPUCLKT1/C1 Slew Rate Control CPUCLKT2/C2 Slew Rate Control AGP_0 Slew Rate Control
PWD 0 1 0 1 0 1 0 1
Description CPUCLKT/C_CS clock slew rate control bits. 01 = strong:10 = normal; 00 = weak CPUCLKT1/C1 clock slew rate control bits. 01 = strong: 10= normal; 00 = weak CPUCLKT2/C2 clock slew rate control bits. 01 = strong: 10= normal; 00 = weak AGP_0 clock slew rate control bits. 01 = strong: 10 = normal; 00 = weak
Byte 22: Slew Rate Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name AGP(2:1) Slew Rate Control PCICLK_F Slew Rate Control PCICLK(7:4) Slew Rate Control PCICLK(3:0) Slew Rate Control
PWD 0 1 0 1 0 1 0 1
Description AGP(2:1) clock slew rate control bits. 01 = strong:10 = normal; 00 = weak PCICLK_F clock slew rate control bits. 01 = strong: 10= normal; 00 = weak PCICLK(7:4) clock slew rate control bits. 01 = strong: 10= normal; 00 = weak PCICLK(3:0) clock slew rate control bits. 01 = strong: 10 = normal; 00 = weak
Byte 23: Slew Rate Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name REF Slew Rate Control IOAPIC(1:0) Slew Rate Control 48MHz Slew Rate Control 24_48MHz Slew Rate Control
PWD 0 1 0 1 0 1 0 1
Description REF clock slew rate control bits. 01 = strong:10 = normal; 00 = weak IOAPIC(1:0) clock slew rate control bits. 01 = strong: 10= normal; 00 = weak 48MHz clock slew rate control bits. 01 = strong: 10= normal; 00 = weak 24_48MHz clock slew rate control bits. 01 = strong: 10 = normal; 00 = weak
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ICS950902
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115C Storage Temperature . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics- Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage V DD = 3.3V +-5% PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Pin Inductance Capacitance1 Transition Time1 Settling Time1 Clk Stabilization1 Delay
1
SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP IDD3.3PD Fi Lpin CIN Cout CINX Ttrans Ts TSTAB tPZH,tPZH tPLZ,tPZH
CONDITIONS
MIN 2 VSS - 0.3
TYP
MAX UNITS VDD + 0.3 V 0.8 5 V mA mA mA 100 280 20 37 7 5 6 45 3 3 3 mA mA mA mA MHz nH pF pF pF ms ms ms ns ns
VIN =V DD VIN= 0 V; Inputs with no pull-up resistors V IN= 0 V; Inputs with no pull-up resistors CL= 0 pF; Select @ 66M CL = Full load @ 133Mhz IREF=2.32 IREF= 5mA VDD=3.3V; Logic Inputs Output pin capacitance X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From V DD = 3.3 V to 1% target Freq. output enable delay (all outputs) output disable delay (all outputs)
-5 -5 -200
156 10
27
1 1
10 10
Guaranteed by design, not 100% tested in production.
0475G--03/23/04
13
Integrated Circuit Systems, Inc.
ICS950902
Electrical Characteristics-CPUCLKC/T
TA = 0 - 70C; VDD = 3.3 V +/-5%; (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Current Source Output ZO VO = VX Impedance VR = 475W +1%; IREF= 2.32mA; Output High Voltage VOH Output High Current I OH I OH = 6*IREF tr VOL = 20%, VOH = 80% Rise Time1 Differential Crossover VX Voltage1 dt VT = 50% Duty Cycle1 1 VT = 50% t sk Skew , CPU to CPU 1 t jcyc-cyc VT = V X Jitter, Cycle-to-cycle Notes: 1 - Guaranteed by design, not 100% tested in production. MIN 3000 0.81 -13.92 270 50 50.2 55 81 1.2 700 55 55 150 200 TYP MAX UNITS Ohm V mA ps % % ps ps
175 45 45
Electrical Characteristics- CPUCLKT/C_CS
TA = 0 - 70C; VDD =2.5 V PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Differential Crossover Voltage1 Duty Cycle Skew Jitter, Cycle-to-cycle Jitter, One Sigma Jitter, Absolute
1
+/-5%; CL = SYMBOL VOH2B VOL2B I OH2B I OL2B t r2B VX dt2B t sk2B t j1s2B
1 1 1 1
20 pF (unless otherwise stated) CONDITIONS I OH = -12.0 mA I OL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, V OH = 2.0 V
MIN 2
TYP
MAX 0.4 -19
19 0.89 45 50 49.6 72 -250 1.6 55 55 175 250 150 250
UNITS V V mA mA ns % % ps ps ps ps
VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
45
t jcy c-cy c2B
1 1
t jabs2B
Guaranteed by design, not 100% tested in production.
0475G--03/23/04
14
Integrated Circuit Systems, Inc.
ICS950902
Electrical Characteristics- SDRAM
TA = 0 - 70C; VDD = 3.3V +/-5%, VDDL PARAMETER SYMBOL Output High Voltage V OH3 Output Low Voltage VOL3 Output High Current I OH3 Output Low Current I OL3 Rise Time1 Fall Time1 Duty Cycle1 Skew window1 t r3 t f3 dt3 t sk3 = 2.5V +/-5%; CL = 30 pF (unless otherwise stated) CONDITIONS MIN TYP I OH = -28 mA 2.4 I OL = 20 mA VOH = 2.0 V VOL = 0.8 V 41 VOL = 0.4 V, V OH = 2.4 V @ 100Mhz VOH = 2.4 V, V OL = 0.4 V @ 100Mhz VT = 1.5 V VT = 1.5 V 45 1.53 1.62 50.2 210 5.6 MAX 0.4 -40 UNITS V V mA mA ns ns % ps ns
2 2 55 250 6
Propagation Time1 (Buffer Tprop VT = 1.5 V In to Output) 1 Guaranteed by design, not 100% tested in production.
Electrical Characteristics- DDRT/C
TA = 0 - 70C; VDDL =2.5 V +/-5%, CL = PARAMETER SYMBOL Output High Voltage V OH3 Output Low Voltage VOL3 Output High Current I OH3 Output Low Current I OL3 Rise Time Fall Time
1 1 1
Duty Cycle Skew (window) Jitter
1
Tr31 Tf31 Dt31 Tsk 1 t jcyc-cyc
1
20 pF (unless otherwise stated) CONDITIONS I OH = -11 mA I OL = 11 mA VOH = 2.0 V VOL = 0.8 V 20% to 80% 80% to 20% VT = 50% VT = 50% VT = 1.5 V
MIN 2
TYP 2282 0.335
MAX 0.4 -12 2.2 2.2 53 250 250
12 0.86 0.65 47 50.2 81 146
UNITS V V mA mA ns ns % ps ps
Guaranteed by design, not 100% tested in production.
0475G--03/23/04
15
Integrated Circuit Systems, Inc.
ICS950902
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = 3.3V +/-5%; CL= 10-30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output Frequency F01 VO = VDD*(0.5) Output Impedance RDSN11 I OH = -1 mA Output High Voltage V OH1 Output Low Voltage VOL1 I OL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = Output High Current I OH1 3.135 V VOL@ MIN = 1.95 V, VOL@ MAX= Output Low Current I OL1 0.4 VOL = 0.4 V, V OH = 2.4 V Rise Time t r11 1 Fall Time VOH = 2.4 V, VOL = 0.4 V t f1 Duty Cycle Skew Jitter
1
MIN 12 2.4
TYP 33.33
MAX 55 0.55
UNITS MHz V V mA mA ns ns % ps ps
-33 30 0.5 0.5 45 1.92 1.92 51 150 157
-33 38 2 2 55 500 250
dt11 t sk11 t jcyc-cyc1
VT = 1.5 V VT = 1.5 V VT = 1.5 V
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - AGP
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =10-30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
MIN 12 2.4 -33 30 0.5 0.5 45
TYP 66.66
MAX 55 0.4 -33 38
UNITS MHz V V mA mA ns ns % ps ps
RDSP11 VOH1 VOL1 I OH1 I OL1 t r11 t f11 dt11 t sk11 t jcyc-cyc1
VO = VDD*(0.5) I OH = -1 mA I OL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.1 VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 VOL = 0.4 V, V OH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
1.92 1.58 50.6 123 133
2 2 55 500 250
Guaranteed by design, not 100% tested in production.
0475G--03/23/04
16
Integrated Circuit Systems, Inc.
ICS950902
Electrical Characteristics - 48MHz, 24MHz
TA = 0 - 70C; VDD = 3.3V +/-5%; CL= 10-30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS VO = VDD*(0.5) Output Frequency FO1 Output Impedance VO = VDD*(0.5) RDSN11 I OH = -1 mA Output High Voltage V OH1 Output Low Voltage VOL1 I OL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = Output High Current I OH1 3.135 V VOL@ MIN = 1.95 V, VOL@ MAX= Output Low Current I OL1 0.4 VOL = 0.4 V, V OH = 2.4 V Rise Time t r1 VOH = 2.4 V, VOL = 0.4 V USB Fall Time t f1 1 Duty Cycle VT = 1.5 V dt1 Jitter
1
MIN 12 2.4
TYP 48
MAX 55 0.55
UNITS MHz V V mA mA ns ns % ps
-29 29 1 1 45 1.29 1.32 52.3 149
-23 27 2 2 55 350
t jcyc-cyc1
VT = 1.5 V
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL=10-20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 VO = VDD*(0.5) Output Impedance RDSP11 Output High Voltage VOH1 I OH = -1 mA Output Low Voltage VOL1 I OL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.1 Output High Current I OH1 VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 Output Low Current I OL1 1 Rise Time VOL = 0.4 V, V OH = 2.4 V t r1 1 VOH = 2.4 V, VOL = 0.4 V Fall Time t f1 1 VT = 1.5 V Duty Cycle dt1 Jitter t jcyc-cyc VT = 1.5 V
1
MIN 20 2.4 -29 29 1 1 45
TYP 14.32
MAX 60 0.4 -23 27 4 4 55 500
1.93 1.97 54 186
UNITS MHz V V mA mA ns ns % ps
Guaranteed by design, not 100% tested in production.
0475G--03/23/04
17
Integrated Circuit Systems, Inc.
ICS950902
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
0475G--03/23/04
18
Integrated Circuit Systems, Inc.
ICS950902
N
c
L
SYMBOL A A1 b c D E E1 e h L N
INDEX AREA
E1
E
12 D h x 45
a
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 18.31 18.55
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
A A1
-Ce
b SEATING PLANE .10 (.004) C
N 56
10-0034
D (inch) MIN .720 MAX .730
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS950902yFLF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
0475G--03/23/04
19
Integrated Circuit Systems, Inc.
ICS950902
N
c
L
INDEX AREA
E1
E
12 D
a
6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS 0 8 0 8 aaa -0.10 -.004 VARIATIONS N D mm. MIN 13.90 MAX 14.10 MIN .547 D (inch) MAX .555
A2 A1
A
-Ce
b SEATING PLANE
56
10-0039
Reference Doc.: JEDEC Publication 95, MO-153
aaa C
Ordering Information
Example:
ICS950902yGLF-T
Designation for tape and reel packaging Lead Free (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
ICS XXXX y G LF- T
0475G--03/23/04
20

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